Modern electronic devices often incorporate one or more integrated circuits. These integrated circuits may comprise a so-called system-on-chip, wherein one or more components of a computing or electronic system are integrated into a single electronic chip. Advances in manufacturing technologies allow a high number of transistors and other logic devices to be integrated into a single chip, thus allowing for advanced functionalities. For example, one or more microprocessors, memory blocks, power management components, external interfaces and functional circuitry may be integrated onto a single silicon substrate. Functional components of these systems may be grouped into what are referred-to as intellectual property (IP) cores. An IP core comprises a reusable unit of electronic chip design that, in most cases, embodies the intellectual property of a single party.
In a system-on-chip, two or more logic units, such as central processing units (CPUs) or Application-Specific Integrated Circuits (ASICs), and/or two or more IP cores may be coupled together on the chip using an interconnect. In this context, an interconnect is a form of system communications bus that allows inter-component communication. In a system-on-chip, the interconnect is integrated into the chip, i.e. comprises an on-chip interconnect. Communications over an on-chip interconnect may form part of transactions between logic units; for example, a first processor may start a transaction that comprises the sending of information to a second processor over an on-chip interconnect.
A combination of increased transistor densities and high clock frequencies means that logic units are subject to a high number of transactions in a given time period, i.e. experience a high transaction load. An on-chip interconnect is also subject to the same high transaction loads. In these cases, there may be a design compromise between high transaction throughput rates and transaction latencies, the latter being the time it takes to complete a transaction including communication over the interconnect. If transaction throughput rates are low, operations on the electronic device may be delayed leading to unresponsiveness. To increase throughput over an interconnect, pipeline stages may be introduced. The pipeline stages may be implemented by one or more of an interconnect controller, one or more IP cores or one or more CPUs. However, pipelining results in increased latencies and leads to transactions being completed out-of-order. Latencies for communications between logic units can lead to errors due to transactions timing out or becoming desynchronised. This is why certain applications and functions have limits reflecting the amount of tolerated latency. For example, certain random access memory sharing systems for an electronic device may only function with specified transaction latencies. Hardware systems thus need to be designed to meet these limits.
In the design and operation of system-on-chip devices, for example to effect the compromise described above, it is useful to have a reliable measurement of a transaction latency. However, latency measurements are often difficult to obtain and are often unreliable.
U.S. Pat. No. 8,032,329 B2 describes a performance monitoring apparatus that may be located on an interconnect of a fabricated integrated circuit. The performance monitoring apparatus has an event generator sub-module that generates monitoring events and event measurements associated with transactions between initiator IP cores and target IP cores over the interconnect. A performance counter module aggregates events and event measurements received from the apparatus into quantities of performance metrics associated with transactions between the IP cores over the interconnect. The performance monitoring apparatus measures latency by repeatedly sampling one event at a time to save silicon area and to reduce hardware complexity. This means, however, that not all latency events will be measured, i.e. only non-overlapping events are monitored and measured. This affects accuracy and reliability.
There is thus a need for accurate and reliable latency measurements for transactions that take place between logic units and components over an on-chip interconnect.